Recently, various kinds of applications for complicated logic operations such as Public Key Infrastructure (PKI) have been developed according to high performance of information processing apparatuses such as computers. In past, there were proposed multi-valued logic function circuits using a MOS (Metal Oxide semiconductor) device. Among them, attention has been paid to a three-valued logic function circuit having good properties in consideration of relation between the number of necessary elements and performance.
As a general method of realizing a three-valued logic function circuit using the MOS device, there has been known a method using a transistor having a threshold voltage changed by controlling a channel dope amount of a MOS transistor. However, in such a method, a p-type MOS transistor or an n-type MOS transistor is used. That is, as the known three-valued logic function circuit, there is no efficient circuit using a CMOS (Complementary MOS). There was no proposal except a current mode CMOS multi-valued logic function circuit in which current constantly flows, which does not have an operation characteristic of CMOS that current does not flows except the switching time (e.g., see Patent Document 1, and Non-Patent Documents 1 to 3, etc.).
Patent Document 1: Japanese Patent Laid-Open Application No. 7-212220
Non-Patent Document 1: WU X W, PROSSER F P, “CMOS ternary logic circuits”, IEE Proc Part G JN: A0160B; ISSN: 0143-7089; CODEN: IPGSEB VOL. 137 NO. 1; PAGE. 21-27; (1990/02)
Non-Patent Document 2: CHANG Y-J, LEE C L, “Synthesis of Multi-Variable MVL Functions Using Hybrid Mode CMOS Logic”, Proc IEEE Int Symp Multiple-Valued LogicJN: B0822B; ISSN: 0195-623XVOL. 24th; PAGE. 35-41; (1994)
Non-Patent Document 3: TEMEL T, MORGUL A, “Multi-valued logic function implementation with novel current-mode logic gates”, IEEE Tnt Symp Circuits Syst JN: A0757AVOL. 2002 NO. Vol. 1; PAGE. I.881-I.864; (2002)
Under such a circumference, the invention disclosed in Patent Document 2 was made by Mr. OLSON, Edgar Danny. According to this invention, there were used plural kinds of a p-type MOS transistor and an n-type MOS transistor having threshold voltages changed by controlling channel dope amounts of the p-type MOS transistor and the n-type MOS transistor, and it was possible to make a multi-valued logic function circuit having an operation characteristic of CMOS that current does not flows except the operating time.
Patent Document 2: Japanese Translation version Patent Publication No. 2002-517937
The case of applying the technique disclosed in Patent Document 2 to the three-valued logic function circuit will be described. That is, in this three-valued logic function circuit, three logic values are represented by −1, 0, 1, corresponding to a negative voltage, a ground voltage (o volt), and a positive voltage, respectively. As shown in FIG. 45, switch circuits SW1, SW2, and SW3, each of which is formed of one or more MOS transistors, are inserted between a power source for supplying a positive voltage and an output terminal, between a ground and the output terminal, and between a power source for supplying a negative voltage and the output terminal. Each of these switch circuits SW1, SW2, and SW3 is formed of arrangement of a p-type MOS transistor and an n-type MOS transistor, and a MOS transistor circuit having an appropriately set threshold voltage, so that each thereof is exclusively turned on according to input voltages corresponding to input logic values −1, 0, 1. In the technique disclosed in Patent Document 2, with such a configuration only, there are 33^2=39=19683 kinds although limiting to all two-variable three-valued logic functions. In addition, there is described that it is possible to realize all three-valued logic operations by appropriate use of two kinds of specific inverters (1, −1, 1) and (1, 1, −1) for the respective inputs, in consideration of the point that it is impossible to realize all.